This invention relates to an integrated semiconductor circuit of the master slice (gate array) type comprising memory cells which are arranged in rows and columns and which are of the read-only type. The memory cells are subdivided into a first and a second group, which first and second group comprise transistors of a first and a second conductivity type, respectively, said semiconductor circuit comprising column selection means for selecting, in response to a column selection signal, an output of either the first or the second group.
An integrated semiconductor circuit of this kind is known from IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 5, October 1985, pp. 1012-1017 "A 240K Transistor CMOS Array with flexible allocation of memory and channels" by Hiromasa Takahashi et al, notably from FIG. 15. The cited article describes a circuit of the gate array type which is also referred to as master slice type. Generally, an integrated semiconductor circuit of the master slice type comprises a plurality of columns of basic cells which are arranged one against the other, connection channels being present between the columns on a central portion of the semiconductor circuit. Since recently integrated semiconductor circuits of the master slice type are available with a so-called "sea of gates" (also referred to as "channel-less gate array" or "high density gate array"); for example, see the article "The CMOS Gate Forest: An Efficient and Flexible High-Performance ASIC Design Environment" by M. Beunder et al. in IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, April 1988, pp. 387-399 where the basic cells are present in the central portion of the semiconductor circuit and the connection channels are formed across the basic cells. An integrated semiconductor circuit of the master slice type with the "sea of gates" permits the integration of a large number of cells because the connection channels occupy little or no additional space. The cited publication by Takahashi describes (see notably FIG. 15 ) a ROM realised in a high density gate array. Said circuit comprises a first group of n-channel memory cells and a second group of p-channel memory cells. Either the n-channel memory cells or the p-channel memory cells are selected by means of a column decoder.